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8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
ADDRESS A MS-0
T CE
CE#
T OEH
T OE
T OES
OE#
WE#
DQ 6 and DQ 2
TWO READ CYCLES
Note: A MS = Most significant address
A MS = A 18
Figure 10: Toggle Bits Timing Diagram
WITH SAME OUTPUTS
1434 F07.0
SIX-BYTE CODE FOR CHIP-ERASE
T SCE
ADDRESSES
555
2AA
555
555
2AA
555
CE#
OE#
T OEH
WE#
RY/BY#
T BY
T BR
DQ 15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
1434 F31.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
WP# must be held in proper logic state (V IH ) 1μs prior to and 1μs after the command sequence.
X can be V IL or V IH , but no other value.
Figure 11: WE# Controlled Chip-Erase Timing Diagram
?2011 Silicon Storage Technology, Inc.
22
DS25041A
05/11
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